A New Improved Model for LDMOS Transistors under Different Gate and Drain Bias Conditions
نویسندگان
چکیده
The behaviour of the capacitances of LDMOS devices as a function of gate and drain bias is analysed using TCAD simulations and S-parameter measurements. Both simulations and measurements revealed that instead of the smooth sigmoïd shape usually seen in MOSTs, the capacitances of LDMOS devices show a distinct ridge at low values of Vds. A full analysis of this phenomena is used to propose a significantly improved macro-model for the DMOS device.
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تاریخ انتشار 2002